Beta release CMC testsuite for Verilog-A LRM 2.2 compliance developed by Tiburon Design Automation. This package contains tests designed to validate an implementation of Verilog-A in a simulator. The tests do not cover all aspects of the language, but are focussed on features necessary to implemented compact device models in Verilog-A. This includes the LRM 2.2 compact model extensions. The files in the documentation directory include: README.txt - this file The Test Philosophy Minimal model complexity to illustrate language feature Netlist should be as generic as possible Use Verilog-A test module to test results if appropriate Test module compares to expected data (stored in table) Pass/Fail reported (with tolerances) Expected results of data available in nutmeg format Installing the tests. Steps 1. Create a test directory. In this example, 'cmc' mkdir cmc 2. Unpack the cmc_testsuite tar file in the cmc directory (VERSION will vary). tar xzf cmc_testsuite_VERSION.tar.gz (note that the file is compressed as well. If your tar executable does not support the -z option, run: uncompress cmc_testsuite_VERSION.tar.gz then tar xf cmc_testsuite_VERSION.tar ). Running a test To run any test, the only necessary step is to include the common directory in the simulator's Verilog-A search path. For example, if the simulator used the environment variable SPICE_MODULE_PATH to search for the files, and this test suite were found in ~/cmc/testsuites, then on kshell or bash shells: export SPICE_MODULE_PATH=~/cmc/testsuite/common:$SPICE_MODULE_PATH If the simulator requires setting a search path for the directory where the netlist is run (e.g., '.'), that should also be set. The files are set up general directories as: analysis - files related to analysis-specific functionality (e.g., noise) common - test files common to all tests documentation - general documentation implementation - implementation-specific features (i.e., tests that show that an analysis-independent specific feature is properly implemented) models - examples of simple compact models and released Verilog-A compact models File extensions All related files will have the same prefix. .net - test netlist .val - netlist used to generate validation results (run only from known-good implementation) .va - associated Verilog-A source code .tbl - data to be used by a table_model function for validation of result .auto -automatically generated file by the test Reference files The reference files are available in a parallel directory tree with the same netlist name with a .raw extension in SPICE3 nutmeg format. Running a test 1. Move to the particular test. E.g., cd testsuites/implementation/limit 2. Ensure that the Verilog-A source file ~/cmc/testsuites/common/test_modules.va is in the simulator's search path. e.g. export SPICE_MODULE_PATH=~/cmc/testsuites/common/test_modules.va Alternatively you copy or symbolically link the file to each directory. 3. Examine the test. For example, the netlist for basic implementation is in basic.net. The comments embedded in the netlist give a description of the test. All of the tests follow the same format: Title: Test basic limit function * [Test] * This test circuit checks that limit works, at a * minimum. * [Test Overview] * This test uses a Verilog-A implementation of a * resistor in series with a resistor. * The limit function is described in the LRM 2.2 * section 10.9. * * If the simulator does not support any limiting * it should return the input argument. * * If the function is not implemented, the simulator * will error out. * [Options] * * [Circuit] vin in 0 0.0 r0 in out 1.0 * [Verilog-A component] x1 out 0 test_module * [Analysis] .dc vin 1 1 1 * [Output] .print dc v(out) * [Expected Results] * The output should be the same as a voltage * divider with two 1.0ohm resistors * * The 'test_constant' module will compare the error * and print out a pass/fail message: x2 out test_constant v_ref=0.5 verbose=1 * [Verilog-A load command] .hdl basic.va .hdl test_modules.va .end The Verilog-A code for this test is very basic: // This module has the minimum implementation // of the limit function. It passes the value // of the input voltage to the simulator's default // limiting algorithm. For this non-limiting case // the simulator should just return the input value. `include "disciplines.vams" module test_module(p,n); electrical p,n; inout p,n; analog I(p,n) <+ $limit(V(p,n)); endmodule The netlist also includes the Verilog-A source file 'test_modules.va'. This file is in the testsuite's common/ directory. This directory must be in the simulator's Verilog-A search path. The tests will output different based on the setting of the verbose flag. This can be overridden in the common/test_modules.va file via the QUIET macro. The test module will compare output to expected values and print ($strobe) an error message if the value is not in range. The tolerance values are adjustable. Note that due to timestep differences, the test is can be fooled. The test module can be set to stop the simulation rather than just print a message by setting the macro FORCE_STOP in the file. The self-test modules can be disabled in the common/test_modules.va file via the ENABLE_SELFTEST macro. 3. Run a simulation: e.g., spice3 -r basic.raw -b basic.net 4. Evaluate the results. Look for output from the test_module similar to: CMC-TEST Passed V(test)=0.5, expected=0.5 The tests are designed to be run from a command line. In most cases (except where an error is expected) the test will complete and the output will include the string: CMC_TEST Passed or CMC_TEST Failed All of the Verilog-A output will have the tag 'CMC_TEST' at the beginning of each string output. This makes it possible to pipe the output through something like grep to only see those strings. Circuit: Title: Test basic limit function CMC-TEST Passed V(test)=0.5, expected=0.5 Circuit: Title: Test basic limit function Date: Sun Jun 4 21:13:19 2006 Title: Test basic limit function DC transfer characteristic Sun Jun 4 21:13:19 2006 --------------------------------------------------------------------------- Index sweep v(out) --------------------------------------------------------------------------- 0 1.000000e+00 5.000000e-01 CPU time since last call: 0.020 seconds. Total CPU time: 0.020 seconds. Current dynamic memory usage = 135168, Dynamic memory limit = 4294967295. The expected output of the test is 0.5 and this is what is seen. 5. Validate the expected results using a plot tool to view the data. Tests designed to fail The following tests should error out due to expected syntax errors or range errors. testsuites/implementation/macros/recursive_macro.net testsuites/implementation/simparam/unsupported_parameter_no_default.net testsuites/implementation/parameters/exclude_complex.net testsuites/implementation/parameters/exclude_integer.net testsuites/implementation/parameters/exclude_real.net testsuites/implementation/parameters/exclude_user_fcn.net