RESPONSE REQUIRED BY: February 22nd MEETING NAME: Compact Models Workshop Meeting number: 284156450 MEETING DATE: March 1-2, 1995 TO: Technology Transfer Managers (E-Mail) Invitees (see attached list) FROM: Reddy Manukonda, Chairman 512/356-3434 Colin McAndrews, Co-Chairman DESCRIPTOR: TECHNOLOGY COMPUTER AIDED DESIGN LOCATION: SEMATECH Conference Room 3-B /EP Austin, Texas PURPOSE: To review state-of-art in compact model generation for CMOS and BJT circuits and provide recommendations to fulfil the SIA roadmap projects. EXPECTED RESULTS: Recommendations on priority areas in compact models for 0.13 and 0.1 micron technologies. OTHER MEETING INFORMATION: Intent: Short presentations to establish industry/university perspectives, to stimulate discussions to work towards baseline requirements for the compact models. Emphasis will be on major flaws/problems in existing approaches and models. The agenda may be changed to accommodate other companies/universities wishing to present their perspective. The workshop intends to bring the viewpoints on international standardization in compact models. Background: As a participant in the SIA Roadmap for Circuit Simulation and Modeling, SEMATECH like to update on what has happened recently. To address the first of the issues identified in the Roadmap, SEMATECH is sponsoring a workshop in Austin, Texas on March 1-2, 1995. The workshop is on compact models for circuit simulation, and the intent is two-fold. First, to convene a group of industry experts on compact models to collectively identify major problems with existing models and approaches to modeling, and thus define minimum standards to which future compact models and model development approaches should be held. Second, to identify for SEMATECH how compact models can best drive advances in the semiconductor industry. AGENDA: Day 1 (Wednesday March 1) ========================= All Coffee/Registration 7:45 am Peter Lloyd SEMATECH Introduction 8:15 Reddy Manukonda Workshop Introduction 8:35 Yannis Tsividis State of MOS Modeling 8:45 Mario Pelella ? IBM perspective 9:00 Dick Klaassen Philips Perspective 9:15 Bill Scott CAD perspective 9:30 Jerry Fossum Predictive compact models 9:45 Shiu-Wuu Lee Intel perspective 10:00 BREAK 10:15 Chenming Hu Standard Models for SPICE 10:30 Zack Lemnios ? ARPA perspective 10:45 Colin McAndrew AT&T perspective 11:00 Ian Getreu ? CAD Perspective 11:15 John Brews ? Perspective 11:30 Narain Arora ? DEC perspective 11:45 LUNCH 12:00 pm All Discussions 1:00 Meeting adjourns 5:00 All Dinner 7:00 Dinner Concludes 9:00 Day 2 (Thursday March 2) ========================= Ed Buturla Break-out Session Introduction 8:15 am ALL Break-out Sessions 8:45 BREAK 10:45 Session Chairs Summary of break-out sessions 11:00 LUNCH 12:00 pm Reddy Manukonda Review and recommendations 1:00 Meeting concludes 2:00 Chair, Company Session ============== ======= Shiu-Wuu Lee, Intel Methodologies for technology mapping: Why silicon and not TCAD for characterization? TBD, IBM, BVT Process/device engineering rule generation B. Gedepally, National Common specification for compact models/ international standardization Ping Yang (?), TI Methodology for circuit library mapping, circuit cell characterization/optimization (area, delay, skew, cross-talk, signal integrity) REGISTRATION FORM: Compact Models Workshop Meeting number: 284156450 March 1-2, 1995